This invention relates to a buffer circuit, more specifically, an output buffer circuit comprising a first inverter circuit with an input terminal and an output terminal which also form the input terminal and the output terminal of the buffer circuit, and with terminals for a first supply voltage, there being inserted between the input terminal and the output terminal of the buffer circuit a series combination of a second inverter circuit and a first capacitor, wherein the second inverter circuit is connected to terminals for a second supply voltage.
Preferably, symmetrical first and second supply voltages are used and the first inverter circuit comprises at least a complementary pair of field effect transistors whose gate and drain connections are mutually coupled, in which the input terminal is coupled to the mutually coupled gate connections and the output terminal is coupled to the mutually coupled drain connections, in which the source connection of the p-channel FET of the complementary pair is coupled to the terminal of the first positive supply voltage and the source connection of the n-channel FET of the pair is coupled to the terminal of the first negative supply voltage.
A buffer circuit of this type is known from DE-A-2929450 reduce the occurrence of in the form of a level shifter. This known circuit has for its object to convert an input voltage level into another, higher output voltage level while the output of the circuit comprising C-MOSFET's is capable of rapidly following voltage changes on the input. In order to increase the edge steepness of the output voltage, an inverter connected to the input terminal is provided. The inverter output terminal is connected to the output terminal of the buffer circuit via a capacitor coupled in series to the output terminal. The inverter is coupled, on one side, to the positive supply voltage terminal and, on the other side, to a connection for a negative supply voltage which is less negative than the negative supply voltage for the complementary pair of FET's. As a result of these measures the combination of the inverter and the capacitor, which forms a differentiator, transfers very rapidly input voltage variations with a limited voltage swing to the output of the circuit, while the final output voltage level is reached in a conventional manner when one of the FET' s conducts in an, of necessity, slightly delayed manner. The switch delay occurring in a thus structured circuit of C-MOSFET's is distinctly smaller than in a circuit comprising exclusively C-MOSFET's.
A disadvantage the prior-art circuit is that the voltage swing at the output is determined, on the one hand, by the positive voltage level and, on the other hand, by the most negative voltage level so that, as a result of the high peak currents flowing through the supply lines during the voltage transitions, annoying disturbing signals occur everywhere in the circuit that comprises the buffer circuit.